Phase-locked loops are extensively used in various electronic applications. A phase-locked loop (PLL) generates an output signal having a phase relative to an input signal (often referred to as a reference signal). The PLL can detect any phase error (difference) between the input signal and the output signal and adjust the phase of the output signal based on the phase error. Oftentimes, a lock detector is implemented to monitor the input signal and the output signal of the PLL to determine whether the PLL has achieved a locked state (condition) that indicates phase alignment between the input signal and the output signal. Although existing lock detectors and associated methods for lock detection for PLLs have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.